1. Field of the Invention
The present invention relates to a voltage conversion circuit for supplying a driving voltage to an integrated circuit, and relates also to a semiconductor integrated circuit device provided with such a voltage conversion circuit.
2. Description of the Prior Art
In general, an integrated circuit that performs arithmetic or other operation in synchronism with an operation clock is designed with ample margins in its specifications to ensure that it operates normally even when there are variations in its characteristics that are inevitable in its manufacturing process or fluctuations in the supplied voltage or in the ambient temperature. Specifically, an integrated circuit is so designed that, even when the delay it produces increases as a result of a variation or fluctuation such as mentioned above or any other factor, an operation of the integrated circuit as a whole is complete within one clock of the operation clock. Moreover, a sufficiently high supply voltage is supplied to the integrated circuit so that it operates normally even when all the factors mentioned above are in the worst condition.
Designing an integrated circuit with ample margins in its specifications and applying a sufficiently high supply voltage to it as described above, however, make it difficult to enhance its speed and to reduce its power consumption. For this reason, efforts have been made to develop a voltage conversion circuit that controls a supply voltage according to the operation status of an integrated circuit so that the integrated circuit is fed with the minimum driving voltage it requires to operate at a given time.
FIG. 21 is a diagram schematically showing an example of the circuit configuration of a conventional voltage conversion circuit. The voltage conversion circuit shown in FIG. 21 is disclosed in Japanese Patent Application Laid-Open No. H10-242831, and is composed of a duty factor control circuit 901, a buffer circuit 902, a filter circuit 903, a critical path circuit 904, a delay circuit 905, a true/false evaluation circuit 906, and an adder 907.
The duty factor control circuit 901 is a circuit that controls the varying of an output voltage in the buffer circuit 902, and is composed of a counter and a comparator. The counter counts up from 0 to 2nxe2x88x921 (for example, when n=6, from 0 to 63) in increments of 1 in synchronism with every period of a clock signal (not shown) fed to it, and feeds its count, in the form of an n-bit signal NA, to the comparator. The count that follows 2nxe2x88x921 is 0. The comparator is fed with, in addition to the signal NA, another n-bit signal NB from the adder 907.
The comparator is a circuit that controls the on/off state of a PMOS transistor M1 and an NMOS transistor M2 that together constitute the buffer circuit 902. The comparator feeds control signals X1 and X2 to the gates of the transistors M1 and M2 respectively. When the signal NA equals 0, the comparator turns the voltage levels of the control signals X1 and X2 to a low level (hereinafter xe2x80x9cL levelxe2x80x9d); when the signals NA and NB are equal, the comparator turns the voltage levels of the control signals X1 and X2 to a high level (hereinafter xe2x80x9cH levelxe2x80x9d).
In the buffer circuit 902, a first supply voltage is applied to the source of the PMOS transistor M1, and a second supply voltage (here the ground voltage) is applied to the source of the NMOS transistor M2. The two transistors have their drains connected together, with the node between them serving as the output end of the buffer circuit 902.
Accordingly, when the control signals X1 and X2 are at L level, the PMOS transistor M1 is on and the NMOS transistor M2 is off. Thus, the output voltage of the buffer circuit 902 is nearly equal to the first supply voltage. By contrast, when the control signals X1 and X2 are at H level, the PMOS transistor M1 is off and the NMOS transistor M2 is on. Thus, the output voltage of the buffer circuit 902 is nearly equal to the second supply voltage (i.e. the ground voltage). That is, the output voltage of the buffer circuit 902 is a pulsating voltage signal Y that rises when the signal NA turns to 0 and that falls when the signal NA becomes equal to the signal NB.
This voltage signal Y is smoothed by the filter circuit 903 composed of an inductor L1 and a capacitor C1, and is thereby formed into an output voltage Z. The output voltage Z is supplied to an internal circuit (not shown) formed on the same circuit board so as to be used as the driving voltage for the internal circuit. The output voltage Z is used also as the supply voltage for the critical path circuit 904.
In the buffer circuit 902, let the period in which the PMOS transistor M1 is on and the NMOS transistor M2 is off (i.e. the period in which the control signals X1 and X2 are at L level) be called the on period T1, and let the period in which the PMOS transistor M1 is off and the NMOS transistor M2 is on (i.e. the period in which the control signals X1 and X2 are at H level) be called the off period T2. Then, the output voltage Z of the filter circuit 903 is generally given by                     Z        =                              T1                          T1              +              T2                                xc3x97          VDD                                    (        1        )            
In the formula above, the on period T1 (the numerator in the right side) represents the pulse width of the voltage signal Y, and the sum T1+T2 of the on period T1 and the off period T2 (the denominator in the right side) represents the pulse period of the voltage signal Y. That is, the output voltage Z can be controlled by controlling the ratio of the pulse width to the pulse period of the voltage signal Y (hereinafter this ratio will be referred to as the xe2x80x9cduty factorxe2x80x9d).
In the voltage conversion circuit configured as described above, the value of the signal NB fed from the adder 907 to the comparator of the duty factor control circuit 901 is varied to vary the on period T1 (the pulse width) and thereby control the duty factor of the voltage signal Y output from the buffer circuit 902. In this way, it is possible to control the driving voltage (the output voltage Z) fed to the internal circuit. (In the following descriptions, this method of controlling the duty factor is called the variable pulse width method.) Moreover, as a means for setting the signal NB at the optimum value at a given time, the operation speed of the critical path circuit 904 is detected.
The critical path circuit 904 is a duplicate circuit of the path that is considered to produce the longest delay within the internal circuit to which the output voltage Z is fed. As described earlier, the output voltage Z of the filter circuit 903 is applied to the critical path circuit 904 as the supply voltage for it. That is, the driving voltage for the internal circuit, i.e. the destination of the voltage supply, is monitored by the critical path circuit 904. Here, it is assumed that the range of voltages on which the critical path circuit 904 can operate is equal to that on which the internal circuit can operate.
When the critical path circuit 904 can operate on the output voltage Z of the filter circuit 903, the critical path circuit 904 feeds predetermined data to the true/false evaluation circuit 906. Here, the true/false evaluation circuit 906 receives the data not only directly from the critical path circuit 904, but also with a delay through the delay circuit 905.
If the true/false evaluation circuit 906 does not receive the data directly from the critical path circuit 904, the true/false evaluation circuit 906 judges that the internal circuit, i.e. the destination of the voltage supply, is not operating normally, and therefore judges that the driving voltage for the internal circuit (i.e. the output voltage Z of the filter circuit 903) is too low. Thus, the true/false evaluation circuit 906 feeds the adder 907 with a signal S1 that instructs it to increment the value of the signal NB by 1 to increase the driving voltage.
If the true/false evaluation circuit 906 receives the delayed data through the delay circuit 905, the true/false evaluation circuit 906 judges that the internal circuit, i.e. the destination of the voltage supply, is operating normally despite the delay given to it, and therefore judges that the driving voltage for the internal circuit is too high. Thus, the true/false evaluation circuit 906 feeds the adder 907 with a signal S2 that instructs it to decrement the value of the signal NB by 1 to decrease the driving voltage.
If the true/false evaluation circuit 906 receives the data directly from the critical path circuit 904 but does not receive the delayed data through the delay circuit 905, the true/false evaluation circuit 906 judges that the internal circuit, i.e. the destination of the voltage supply, is receiving the optimum driving voltage at the time. Thus, the true/false evaluation circuit 906 feeds the adder 907 with neither the signal S1 nor the signal S2.
When the true/false evaluation circuit 906 outputs the signal S1, the adder 907 feeds the duty factor control circuit 901 with a value obtained by adding 1 to the current value of the signal NB. By contrast, when the true/false evaluation circuit 906 outputs the signal S2, the adder 907 feeds the duty factor control circuit 901 with a value obtained by adding xe2x88x921 to the current value of the signal NB.
In this way, in the voltage conversion circuit configured as described above, the critical path circuit 904, the delay circuit 905, and the true/false evaluation circuit 906 detect the operation speed of the internal circuit, i.e. the destination of the voltage supply, and control the duty factor of the voltage signal Y in such a way as to decrease the driving voltage for the internal circuit (i.e. the output voltage Z) if the detected operation speed is too fast and increase the driving voltage for the internal circuit (i.e. the output voltage Z) if the detected operation speed is too slow.
It is true that the voltage conversion circuit configured as described above contributes to the reduction of the power consumption of the integrated circuit, because it permits the internal circuit constituting the integrated circuit to be fed with the minimum driving voltage on which the internal circuit can operate at a given time according to the operation status of the internal circuit. It is also true that this voltage conversion circuit is useful as a voltage step-down circuit for common integrated circuits, because it permits the output voltage Z to be varied in a wide range.
Incidentally, a very effective way to further reduce the power consumption of the internal circuit is to reduce the supply voltage for the devices themselves that constitute the internal circuit. For example, the power consumption of an internal circuit employing devices that operate on a supply voltage of 0.5 V is {fraction (1/36)} of the power consumption of an internal circuit employing devices that operate on a supply voltage of 3 V. In this way, by reducing the supply voltage for and the load current through the internal circuit, it is possible to further reduce power consumption.
As the power consumption of the internal circuit decreases, the proportion of the power consumption of the voltage conversion circuit to that of the integrated circuit as a whole increases relatively. Therefore, to further reduce the power consumption of the integrated circuit as a whole, it is essential to reduce the power consumption of the voltage conversion circuit itself
Here, one possible means of reducing the power consumption of the voltage conversion circuit itself configured as described above is restricting the range in which the output voltage Z can be varied, because this helps simplify the control required and reduce the scale of the duty factor control circuit 901, the adder 907, and other circuit blocks.
For example, in a case where the voltage conversion circuit receives an external source voltage of about 3 V and supplies power to an internal circuit that operates on 0.5 V, the voltage that the voltage conversion circuit outputs to the internal circuit need not be so high as to be close to the voltage that the voltage conversion circuit receives. Moreover, the devices constituting the internal circuit have their respective optimum operating voltages, and therefore it is still possible to cope with variations inevitable in their manufacturing process and changes in the operating environment even if the range in which the output voltage Z can be varied is restricted, as long as it is restricted in the vicinity of the operating voltages of those devices. In this way, by restricting the range in which the output voltage Z can be varied, it is possible to reduce the circuit scale of the voltage conversion circuit and thereby reduce its power consumption.
However, in the voltage conversion circuit adopting the variable pulse width method, in which the value of the signal NB fed from the adder 907 to the comparator is varied to vary the on period T1 (the pulse width) and thereby control the duty factor of the output signal Y output from the buffer circuit 902, even when the range in which the output voltage Z can be varied is restricted, it is still necessary to provide a counter circuit that operates at high speed.
For example, in the conventional voltage conversion circuit configured as described above, the counter circuit operates at 2n times (i.e., when n=6, 64 times) the frequency of the voltage signal Y. The counter circuit, operating at such high speed, thus increases the power consumption of the voltage conversion circuit itself, but, to permit the output voltage Z to be varied with high accuracy, it is inevitable to keep the operation speed of the counter circuit sufficiently high.
For this reason, in the conventional voltage conversion circuit adopting the variable pulse width method, even when the range in which the output voltage Z can be varied is restricted for an internal circuit that can operate on a low voltage, the operation speed of the counter circuit needs to be kept sufficiently high. This makes it impossible to achieve satisfactory reduction of the power consumption of the voltage conversion circuit itself.
An object of the present invention is to provide a voltage conversion circuit suitable for lower output voltage applications, and to provide a semiconductor integrated circuit device provided with such a voltage conversion circuit.
To achieve the above object, according to the present invention, a voltage conversion circuit is provided with a pulse generator for generating a pulse signal having a fixed pulse width and a variable pulse period. Here, the output voltage is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator.